• Multilayer circuit boards

- FEATURES MANUFACTURE MULTILAYER
- GENERAL TOLERANCES

The ever increasing complexity, along with the minimisation of the space in the printed circuit boards, have been the main reasons for the strong development of multiple layer circuits. During the last years, the progression in the manufacture of this type of circuits has been constant in Lab Circuits.

The classical structure of a multiple layer circuit board is based on the so called nuclei consisting of the internal faces of ground and signal and the faces of the components and conventional welds on the outside.

The nuclei are formed by an FR4 material (fibreglass and epoxy) sheet with two external copper layers.

The nucleus has its own entity within the manufacturing process, just up to the time of pressing. It goes through a process of lamination, insolation, and chemical treatment to finish by creating a sole structure combining the nuclei with pre-preg (fibreglass and epoxy) sheets and copper films for outer closure. This "unifying" is achieved through high temperature pressing. Once pressed, this structure receives the same treatment as a two layer circuit board.

The features which differentiate the multiple layer are:

• The number of internal layers: from 2 to 16 in the case of Lab Circuits.
• The copper micrage either inside or outside.

The final thickness of the circuit board basically depends on the number of nuclei and their thickness and on the number of pre-preg sheets used.

The new technologies have allowed the creation of interconnections between the nuclei of multiple layer circuit boards through internal holes: the blind vias and the buried vias. The blind vias connect one of the external faces to a specific internal face, without the hole completely passing through the circuit board. The buried vias interconnect internal faces, without the hole appearing on the outer faces.

In order to classify the printed circuits’ difficulty we use the following parameters:

- CLASS
Is the dimensional characteristics set of the different elements that compose the printed circuit board image.

- RING CHECK
Makes reference to the copper ring between the hole and its pad. This parameter will determine the difficulty of trim between the hole and the image of the circuit.

- TOLERANCES
Made reference to the tolerance level of the different processes and materials.

The total of these 3 concepts will define the manufacture difficulty and therefore the price of the circuit.

PARAMETERS MANUFACTURE MULTILAYER

		CLASS 3	CLASS 4	CLASS 5	CLASS 6	CLASS 7
Minimum plated through hole diameter		20 mil	12 mil	12 mil	8 mil	6 mil
Minimum non plated through hole diameter		24 mil	16 mil	16 mil	12 mil	10 mil
Aspect/Ratio		5	5	6	8	13 (maximun thickness 80 mils)
Minimum outerlayer trace/spacing width		12 mil (½ oz) 12 mil (1 oz) 14 mil (2 oz)	8 mil (½ oz) 8 mil (1 oz) 10 mil (2 oz)	6 mil (½ oz) 6 mil (1 oz) 8 mil (2 oz)	5 mil (½ oz) 6 mil (1 oz) 7 mil (2 oz)	4 mil (½ oz )
Minimum innerlayer trace/spacing width		10 mil (½ oz) 12 mil (1 oz) 12 mil (2 oz)	6 mil (½ oz) 8 mil (1 oz) 8 mil (2 oz)	5 mil (½ oz) 6 mil (1 oz) 7 mil (2 oz)	4 mil (½ oz) 5 mil (1 oz) 6 mil (2 oz)	3 mil (½ oz) 4 mil (1 oz)
Minimum Outer layer annular ring		9 mil	7 mil	5 mil	4 mil	3 mil
Minimum Signal inner layer annular ring		10 mil	9 mil	8 mil	6 mil	5 mil
Minimum annular spacing in ground plane		16 mil	16 mil	12 mil	10 mil	8 mil
Minimum microvia diameter				4 mil (max. thickness 4 mils)	3 mil (max. thickness 3 mils)	3 mil (max. thickness 3 mils)
Microvia surface pad				14 mil	12 mil	10 mil
Microvia landing pad				14 mil	12 mil	10 mil
Minimum wall between microvia and through hole / blind/ buried				9 mil	6 mil	4 mil
Minimum wall between microvias				9 mil	6 mil	4 mil
Minimum wall between microvias into consecutive levels				9 mil	6 mil	4 mil

MULTILAYER GENERAL TOLERANCES

		STANDARD	SPECIAL
Outer layer trace/spacing width		±20% (½ oz ) ±25% (1-2 oz )	±10% (½ oz ) ±15% (1 - 2 oz)
Inner layer trace/spacing width		±20% (½ - 1 oz) ±25% (2 oz)	±10% (½ oz ) ±15% (1 - 2 oz )
Plated hole diameter		+4 mil / -2 mil (or equivalent)	+4 mil / -0,0 mil ±2 mil
Non plated hole diameter		+4 mil / -0,0 mil (or equivalent)	±1.4 mil (or equivalent)
Scoring to copper clearance		Min. 40 mil.	Min. 30 mil
Scoring positioning		± 4 mil	± 3 mil
Scoring remaining thickness		± 4 mil	± 2 mil
Board size		± 6 mil.	± 4 mil.
Total thickness tolerance		±10 %	±5 %
Dielectric thickness		±10 %	±5 %
Finished plated hole copper thickness		Average: 0.7 oz Minimum: 0.6 oz	Average: 1 oz Minimum: 0.86 oz
Blind/buried plated hole copper thickness		Average: 0.4 oz. Minimum: 0.37 oz.	Average : 0.7 oz. Minimum: 0.6 oz.
Microvia Plated hole copper thickness		Mitja: 0.4 oz. Mínim:0.37 oz.	Mitja: 0.7 oz. Mínim: 0.6 oz.
Mínimum wall between same net plated through holes		12 mil.	10 mil.
Minimum wall between different net plated through holes		16 mil.	14 mil.
Minimum wall between non plated thruough holes		10 mil.	8 mil.
Minimum annular ring non plated hole		10 mil.	8 mil.
Track to non plated through hole minimum spacing		8 mil.	6 mil.
Track to board edge minimum spacing		8 mil.	6 mil.
Offset between board edge and drill		Max. 6 mil.	Max. 4 mil.
Offset between drill to outlayer pad		Max. 4 mil.	Max. 3 mil.
Offset between drill to innerlayer pad		Max. 6 mil.	Max. 5 mil.
Offset between layers		Max. 4 mil.	Max. 3 mil.
Soldermask feature tolerance		Max. 6 mil.	Max. 3 mil.
Soldermask min Dam size		3 mil.	-
Photoimageable soldermask clearance		3 mil.	-
Silkscreened soldermask clearance		8 mil.	6 mil.
Legend minimum line		5 mil.	4 mil.
Conductive ink (graphite) overlapping		8 mil.	5 mil.
Conductive ink (graphite) spacing		20 mil.	16 mil.
Conductive ink to pad spacing		16 mil.	12 mil.
Peel-off mask overlapping		40 mil.	28 mil.
Peel-off mask to pad spacing		40 mil.	28 mil.
Peel-off mask to board edge spacing		40 mil.	28 mil.
Maximum peel-off mask filled hole		71 mil.	79 mil.
Bow and twist		Maxim 1%	Maxim 0,5 %
Insulation resistance		Minimum 0,5 MOhm	Minimum 2,0 MOhm
Continuity		Maxim 10 Ohms	-
Electrical strenght		750 V/mil (30 V/µm.) segons MIL-13949 H	-
Ionic contamination		Max. 1µg Eq. CINa/cm2	Max. 0,8 µg Eq. CINa/cm2
Other features		See spec. IPC-A-600 Rev.E 8-95	-