• Multilayer circuit boards

- FEATURES MANUFACTURE MULTILAYER
- GENERAL TOLERANCES

The ever increasing complexity, along with the minimisation of the space in the printed circuit boards, have been the main reasons for the strong development of multiple layer circuits. During the last years, the progression in the manufacture of this type of circuits has been constant in Lab Circuits.

The classical structure of a multiple layer circuit board is based on the so called nuclei consisting of the internal faces of ground and signal and the faces of the components and conventional welds on the outside.

The nuclei are formed by an FR4 material (fibreglass and epoxy) sheet with two external copper layers.

The nucleus has its own entity within the manufacturing process, just up to the time of pressing. It goes through a process of lamination, insolation, and chemical treatment to finish by creating a sole structure combining the nuclei with pre-preg (fibreglass and epoxy) sheets and copper films for outer closure. This "unifying" is achieved through high temperature pressing. Once pressed, this structure receives the same treatment as a two layer circuit board.

The features which differentiate the multiple layer are:

• The number of internal layers: from 2 to 16 in the case of Lab Circuits.
• The copper micrage either inside or outside.

The final thickness of the circuit board basically depends on the number of nuclei and their thickness and on the number of pre-preg sheets used.

The new technologies have allowed the creation of interconnections between the nuclei of multiple layer circuit boards through internal holes: the blind vias and the buried vias. The blind vias connect one of the external faces to a specific internal face, without the hole completely passing through the circuit board. The buried vias interconnect internal faces, without the hole appearing on the outer faces.

In order to classify the printed circuits’ difficulty we use the following parameters:

- CLASS
Is the dimensional characteristics set of the different elements that compose the printed circuit board image.

- RING CHECK
Makes reference to the copper ring between the hole and its pad. This parameter will determine the difficulty of trim between the hole and the image of the circuit.

- TOLERANCES
Made reference to the tolerance level of the different processes and materials.

The total of these 3 concepts will define the manufacture difficulty and therefore the price of the circuit.

PARAMETERS MANUFACTURE MULTILAYER

		CLASS 3	CLASS 4	CLASS 5	CLASS 6	CLASS 7
Minimum plated through hole diameter		0,50 mm	0,30 mm	0,30 mm	0,20 mm	0,15 mm
Minimum non plated through hole diameter		0,60 mm	0,40 mm	0,40 mm	0,30 mm	0,25 mm
Aspect/Ratio		5	5	6	8	13 (maximun thickness 2 mm)
Minimum outerlayer trace/spacing width		0,30 mm (17 µ m) 0,30 mm (35 µ m) 0,35 mm (70 µ m)	0,20 mm (17 µ m) 0,20 mm (35 µ m) 0,25 mm (70 µ m)	0,15 mm (17 µ m) 0,15 mm (35 µ m) 0,20 mm (70 µ m)	0,125 mm (17 µm) 0,15 mm (35 µm) 0,175 mm (70 µm)	0,100 mm (17 µ)
Minimum innerlayer trace/spacing width		0,25 mm (17 µ m) 0,30 mm (35 µ m) 0,30 mm (70 µ m)	0,15 mm (17 µ m) 0,20 mm (35 µ m) 0,20 mm (70 µ m)	0,125 mm (17 µ m) 0,15 mm (35 µ m) 0,175 mm (70 µ m)	0,10 mm (17 µ m) 0,125 mm (35 µ m) 0,15 mm (70 µ m)	0,075 mm (17 µ m) 0,100 mm (35 µ m)
Minimum Outer layer annular ring		0.22 mm	0.17 mm	0.13 mm	0.10 mm	0.075 mm
Minimum Signal inner layer annular ring		0.25 mm	0.22 mm	0.19 mm	0.15 mm	0.125 mm
Minimum annular spacing in ground plane		0.40 mm	0.40 mm	0.30 mm	0.25 mm	0.20 mm
Minimum microvia diameter				0,10 mm (max. thickness 0.1 mm)	0,075 mm (max. thickness 0.065 mm)	0,075 mm (max. thickness 0.065 mm)
Microvia surface pad				0.35 mm	0.30 mm	0.25 mm
Microvia landing pad				0.30 mm	0.25 mm	0.20 mm
Minimum wall between microvia and thru hole / blind/ buried				0.22 mm	0.15 mm	0.10 mm
Minimum wall between microvias				0.23 mm	0.15 mm	0.10 mm
Minimum wall between microvias in two levels				0.23 mm	0.15 mm	0.10 mm

MULTILAYER GENERAL TOLERANCES

		STANDARD	SPECIAL
Outer layer trace/spacing width		±25% (35-70 µm) ±20% (17 µm )	±15% (35-70 µm) ±10% (17 µm)
Inner layer trace/spacing width		±25% (70 µm ) ±20% (17-35 µm )	±15% (35-70 µm) ±10% (17 µm)
Plated hole diameter		+0,10 mm / -0,05 mm (or equivalent)	+0,10 mm / -0,0 mm (or equivalent)
Non plated hole diameter		+0,10 mm / -0,0 mm (or equivalent)	±0,035 mm (or equivalent)
Scoring to copper clearance		Min. 1,0 mm.	Min. 0,75 mm.
Scoring positioning		±0,10 mm	±0,075 mm
Scoring remaining thickness		±0,15 mm	±0,075 mm
Board size		± 0,15 mm.	± 0,10 mm.
Total thickness tolerance		±10 %	±5 %
Dielectric thickness		±10 %	±5 %
Finished plated hole copper thickness		Average: 25 µm Minim: 20 µm	Average: 35 µm Mínim: 30 µm
Blind/buried plated hole copper thickness		Average: 15 µm Minim: 13 µm	Mitja: 25 µm Mínim: 20 µm
Microvia Plated hole copper thickness		Mitja: 15 µm Mínim:13 µm	Mitja: 25 µm Mínim: 20 µm
Mínimum wall between same net plated through holes		0.30 mm	0.25 mm
Minimum wall between different net plated through holes		0,40 mm.	0,35 mm.
Minimum wall between non plated thruough holes		0,25 mm.	0,20 mm.
Minimum annular ring non plated hole		0,25 mm	0,20 mm
Track to non plated through hole minimum spacing		0,20 mm	0,15 mm
Track to board edge minimum spacing		0,20 mm	0,15 mm
Offset between board edge and drill		Max. 0,15 mm.	Max. 0,10 mm.
Offset between drill to outlayer pad		Max. 0,10 mm.	Max. 0,075 mm.
Offset between drill to innerlayer pad		Max. 0,15 mm.	Max. 0,12 mm.
Offset between layers		Max. 0,10 mm.	Max. 0,075 mm.
Soldermask feature tolerance		Max. 0,15 mm.	Max. 0,075 mm.
Soldermask min Dam size		0.075 mm
Photoimageable soldermask clearance		0.075 mm
Silkscreened soldermask clearance		0,20 mm	0,15 mm
Legend minimum line		0,125 mm	0,10 mm
Conductive ink (graphite) overlapping		0,20 mm	0,125 mm
Conductive ink (graphite) spacing		0,50 mm	0,40 mm
Conductive ink to pad spacing		0,40 mm	0,30 mm
Peel-off mask overlapping		1 mm	0,70 mm
Peel-off mask to pad spacing		1 mm	0,70 mm
Peel-off mask to board edge spacing		1 mm	0,70 mm
Maximum peel-off mask filled hole		1.80 mm	2 mm
Bow and twist		Maxim 1%	Maxim 0,5 %
Insulation resistance		Minim 0,5 MOhm	Minim 2,0 MOhm
Continuity		Maxim 10 Ohms	-
Electrical strength		750 V/mil (30 V/µm.) segons MIL-13949 H	-
Ionic contamination		Max. 1µg Eq. CINa/cm2	Max. 0,8 µg Eq. CINa/cm2
Other features		See spec. IPC-A-600 Rev.G jul-04	-