• Multilayer circuit boards

- FEATURES MANUFACTURE MULTILAYER
- GENERAL TOLERANCES

The ever increasing complexity, along with the minimisation of the space in the printed circuit boards, have been the main reasons for the strong development of multiple layer circuits. During the last years, the progression in the manufacture of this type of circuits has been constant in Lab Circuits.

The classical structure of a multiple layer circuit board is based on the so called nuclei consisting of the internal faces of ground and signal and the faces of the components and conventional welds on the outside.

The nuclei are formed by an FR4 material (fibreglass and epoxy) sheet with two external copper layers.

The nucleus has its own entity within the manufacturing process, just up to the time of pressing. It goes through a process of lamination, insolation, and chemical treatment to finish by creating a sole structure combining the nuclei with pre-preg (fibreglass and epoxy) sheets and copper films for outer closure. This "unifying" is achieved through high temperature pressing. Once pressed, this structure receives the same treatment as a two layer circuit board.

The features which differentiate the multiple layer are:

• The number of internal layers: from 2 to 16 in the case of Lab Circuits.
• The copper micrage either inside or outside.

The final thickness of the circuit board basically depends on the number of nuclei and their thickness and on the number of pre-preg sheets used.

The new technologies have allowed the creation of interconnections between the nuclei of multiple layer circuit boards through internal holes: the blind vias and the buried vias. The blind vias connect one of the external faces to a specific internal face, without the hole completely passing through the circuit board. The buried vias interconnect internal faces, without the hole appearing on the outer faces.

In order to classify the printed circuits’ difficulty we use the following parameters:

- CLASS
Is the dimensional characteristics set of the different elements that compose the printed circuit board image.

- RING CHECK
Makes reference to the copper ring between the hole and its pad. This parameter will determine the difficulty of trim between the hole and the image of the circuit.

- TOLERANCES
Made reference to the tolerance level of the different processes and materials.

The total of these 3 concepts will define the manufacture difficulty and therefore the price of the circuit.

FEATURES MANUFACTURE MULTILAYER

		CLASS 3	CLASS 4	CLASS 5	CLASS 6	CLASS 7
Minimum plated hole		0,50 mm	0,30 mm	0,30 mm	0,20 mm	0,15 mm
Minimum non plated hole		0,60 mm	0,40 mm	0,40 mm	0,30 mm	0,25 mm
Aspect/Ratio		5	5	6	8	13 (maximun thickness 2 mm)
Outer layer minimum conductor width/spacing (thickness copper foil ).		0,30 mm (17 µ m) 0,30 mm (35 µ m) 0,35 mm (70 µ m)	0,20 mm (17 µ m) 0,20 mm (35 µ m) 0,25 mm (70 µ m)	0,15 mm (17 µ m) 0,15 mm (35 µ m) 0,20 mm (70 µ m)	0,125 mm (17 µm) 0,15 mm (35 µm) 0,175 mm (70 µm)	0,100 mm (17 µ)
Inner layer minimum conductor width/spacing (thickness copper foil)		0,25 mm (17 µ m) 0,30 mm (35 µ m) 0,30 mm (70 µ m)	0,15 mm (17 µ m) 0,20 mm (35 µ m) 0,20 mm (70 µ m)	0,125 mm (17 µ m) 0,15 mm (35 µ m) 0,175 mm (70 µ m)	0,10 mm (17 µ m) 0,125 mm (35 µ m) 0,15 mm (70 µ m)	0,075 mm (17 µ m) 0,100 mm (35 µ m)
Outer layer minimum annular ring		0.22 mm	0.17 mm	0.13 mm	0.10 mm	0.075 mm
Signal inner layer minimum annular ring		0.25 mm	0.22 mm	0.19 mm	0.15 mm	0.125 mm
Minimum annular spacing in ground plane		0.40 mm	0.40 mm	0.30 mm	0.25 mm	0.20 mm
Minimum diameter microvia		0,10 mm	0,10 mm	0,10 mm	0.075 mm	0.075 mm
Microvia surface pad		0.35 mm	0.35 mm	0.35 mm	0.30 mm	0.25 mm
Microvia landing pad		0.35 mm	0.35 mm	0.35 mm	0.30 mm	0.25 mm
Maximun isolation thickness in microvias (must be smaller than microvia diameter)		0.065 mm	0.065 mm	0.065 mm	0.10 mm	0.10 mm
Minimum distance between thu-hole and microvia		0.45 mm	0.45 mm	0.45 mm	0.40 mm	0.275 mm
Minimum distance between buried hole and microvia		0.45 mm	0.45 mm	0.45 mm	0.40 mm	0.275 mm
Minimum distance between microvias		0.60 mm	0.55 mm	0.50 mm	0.45 mm	0.35 mm
Minimum distance between microvias in two levels		0.35 mm	0.35 mm	0.35 mm	0.30 mm	0.25 mm
Minimum buried drill		0.30 mm	0.30 mm	0.30 mm	0.20 mm	0.15 mm

GENERAL TOLERANCES

		STANDARD	SPECIAL
Conductor width in outer layer (thickness copper foil)		±25% (35-70 µm) ±20% (17 µm )	±15% (35-70 µm) ±10% (17 µm)
Conductor width in inner layers (thickness copper foil)		±25% (70 µm ) ±20% (17-35 µm )	±15% (35-70 µm) ±10% (17 µm)
Plated hole diameter		+0,10 mm / -0,05 mm (or equivalent)	+0,10 mm / -0,0 mm (or equivalent)
Unplated hole diameter		+0,10 mm / -0,0 mm (or equivalent)	±0,035 mm (or equivalent)
Copper clearance for scoring		Min. 1,0 mm.	Min. 0,75 mm.
Scoring positional accuracy		±0,10 mm	±0,075 mm
Scoring remaining thickness		±0,15 mm	±0,075 mm
Outers dimensions		± 0,15 mm.	± 0,10 mm.
Thickness tolerance		±10 %	±5 %
Dielectric thickness		±10 %	±5 %
Plating thickness, copper, holes.		Average: 25 µm Minim: 20 µm	Average: 35 µm Mínim: 30 µm
Plating thickness, copper, buried vias		Average: 15 µm Minim: 13 µm	Mitja: 25 µm Mínim: 20 µm
Wall between neighbour Plated Holes		0,40 mm.	0,35 mm.
Wall between neighbour nonplated holes.		0,25 mm.	0,20 mm.
Wall between neighbour nonplated holes.		0,25 mm	0,20 mm
Minimum annular ring in nonplated holes		0,20 mm	0,15 mm
Conductor to boardedge minimum spacing		0,20 mm	0,15 mm
Drilling to outline misalignement		Max. 0,15 mm.	Max. 0,10 mm.
Drill to pad misalingnement (outerlayer)		Max. 0,10 mm.	Max. 0,075 mm.
Drill to pad misalignement (innerlayer)		Max. 0,15 mm.	Max. 0,12 mm.
Layer to layer misalignement		Max. 0,10 mm.	Max. 0,075 mm.
Soldermask to pad misalignement		Max. 0,15 mm.	Max. 0,075 mm.
Soldermask minimum line (SMT)		0,10 mm	0,075 mm
Photoimageable soldermask clearance		0,10 mm	0,075 mm
Silkscreened soldermask clearance		0,20 mm	0,15 mm
Legend minimum line		0,15 mm	0,125 mm
Conductive ink (graphite) overlapping		0,20 mm	0,125 mm
Conductive ink (graphite) spacing		0,50 mm	0,40 mm
Conductive ink-pad spacing		0,40 mm	0,30 mm
Peel-off mask overlapping		1 mm	0,60 mm
Peel-off mask-pad spacing		0.5 mm	0,50 mm
Peel-off mask-board edge spacing		0.4 mm	0,40 mm
Maximum peel-off mask filled hole		2 mm	2 mm
Bow and twist		Maxim 1%	Maxim 0,5 %
Insulation resistance		Minim 0,5 MOhm	Minim 2,0 MOhm
Continuity		Maxim 10 Ohms	-
Electrical strength		750 V/mil (30 V/µm.) segons MIL-13949 H	-
Ionic contamination		Max. 1µg Eq. CINa/cm2	Max. 0,8 µg Eq. CINa/cm2
For other features		See spec. IPC-A-600 Rev.G jul-04	-