• Double side circuit boards
- FEATURES MANUFACTURE DOUBLE SIDE
- GENERAL TOLERANCES
In order to classify the printed circuits’ difficulty we use the following parameters:
- CLASS
Is the dimensional characteristics set of the different elements that compose the printed circuit board image.
- RING CHECK
Makes reference to the copper ring between the hole and its pad. This parameter will determine the difficulty of trim between the hole and the image of the circuit.
- TOLERANCES
Made reference to the tolerance level of the different processes and materials.
The total of these 3 concepts will define the manufacture difficulty and therefore the price of the circuit.
FEATURES MANUFACTURE DOUBLE SIDE
|
|
CLASS 3 |
CLASS 4 |
CLASS 5 |
CLASS 6 |
CLASS 7 |
| Minimum plated hole |
|
0,50 mm |
0,30 mm |
0,30 mm |
0,20 mm |
0,15 mm |
| Minimum non plated hole |
|
0,60 mm |
0,40 mm |
0,40 mm |
0,30 mm |
0,25 mm |
| Aspect/Ratio |
|
5 |
5 |
6 |
8 |
13
(maximum thickness 2 mm) |
Outer layer minimum
conductor with/spacing.
(thickness copper foil.) |
|
0,30 mm (17 µ )
0,30 mm (35 µ )
0,35 mm ( 70 µ ) |
0,20 mm (17 µ )
0,20 mm (35 µ )
0,25 mm ( 70 µ ) |
0,150 mm (17 µ)
0,150 mm (35 µ)
0,200 mm (70 µ ) |
0,125 mm (17 µ)
0,150 mm (35 µ)
0,175 mm (70 µ ) |
0,100 mm (17 µ)
|
minimum annular ring
|
|
0.22 mm |
0.17 mm |
0.13mm |
0.10mm |
0.075 mm |
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GENERAL TOLERANCES
|
|
STANDARD |
SPECIAL |
Conductor width in outer layer
(thickness copper foil) |
|
±25% (35-70 µm)
±20% (17 µm ) |
±15% (35-70 µm)
±10% (17 µm) |
Conductor width in inner layers
(thickness copper foil) |
|
±25% (70 µm )
±20% (17-35 µm ) |
±15% (35-70 µm)
±10% (17 µm) |
| Plated hole diameter |
|
+0,10 mm / -0,05 mm
(or equivalent)
|
+0,10 mm / -0,0 mm
(or equivalent)
|
| Unplated hole diameter |
|
+0,10 mm / -0,0 mm
(or equivalent)
|
±0,035 mm
(or equivalent)
|
| Copper clearance for scoring |
|
Min. 1,0 mm. |
Min. 0,75 mm. |
| Scoring positional accuracy |
|
±0,10 mm |
±0,075 mm |
| Scoring remaining thickness |
|
±0,15 mm
|
±0,075 mm
|
| Outers dimensions |
|
± 0,15 mm.
|
± 0,10 mm. |
| Thickness tolerance |
|
±10 % |
±5 % |
| Dielectric thickness |
|
±10 % |
±5 % |
| Plating thickness, copper, holes. |
|
Average: 25 µm
Minim: 20 µm |
Average: 35 µm
Mínim: 30 µm |
Plating thickness,
copper, buried vias |
|
Average: 15 µm
Minim: 13 µm |
Mitja: 25 µm
Mínim: 20 µm |
| Wall between neighbour Plated Holes |
|
0,40 mm. |
0,35 mm. |
| Wall between neighbour nonplated holes. |
|
0,25 mm. |
0,20 mm. |
Wall between
neighbour nonplated holes. |
|
0,25 mm
|
0,20 mm
|
| Minimum annular ring in nonplated holes |
|
0,20 mm
|
0,15 mm
|
Conductor to boardedge
minimum spacing |
|
0,20 mm
|
0,15 mm
|
| Drilling to outline misalignement |
|
Max. 0,15 mm.
|
Max. 0,10 mm.
|
Drill to pad misalingnement
(outerlayer) |
|
Max. 0,10 mm.
|
Max. 0,075 mm.
|
Drill to pad misalignement
(innerlayer) |
|
Max. 0,15 mm. |
Max. 0,12 mm.
|
| Layer to layer misalignement |
|
Max. 0,10 mm.
|
Max. 0,075 mm.
|
Soldermask to pad
misalignement |
|
Max. 0,15 mm. |
Max. 0,075 mm. |
Soldermask minimum line
(SMT) |
|
0,10 mm
|
0,075 mm
|
| Photoimageable soldermask clearance |
|
0,10 mm
|
0,075 mm
|
| Silkscreened soldermask clearance |
|
0,20 mm
|
0,15 mm
|
| Legend minimum line |
|
0,15 mm
|
0,125 mm
|
| Conductive ink (graphite) overlapping |
|
0,20 mm
|
0,125 mm
|
| Conductive ink (graphite) spacing |
|
0,50 mm |
0,40 mm |
| Conductive ink-pad spacing |
|
0,40 mm |
0,30 mm |
| Peel-off mask overlapping |
|
1 mm
|
0,60 mm
|
| Peel-off mask-pad spacing |
|
0.5 mm |
0,50 mm |
Peel-off mask-board
edge spacing |
|
0.4 mm |
0,40 mm |
| Maximum peel-off mask filled hole |
|
2 mm |
2 mm |
| Bow and twist |
 |
Maxim 1% |
Maxim 0,5 % |
| Insulation resistance |
 |
Minim 0,5 MOhm |
Minim 2,0 MOhm |
| Continuity |
 |
Maxim 10 Ohms |
- |
| Electrical strength |
 |
750 V/mil (30 V/µm.)
segons MIL-13949 H |
- |
| Ionic contamination |
 |
Max. 1µg Eq. CINa/cm2 |
Max. 0,8 µg Eq. CINa/cm2 |
| For other features |
 |
See spec.
IPC-A-600 Rev.G jul-04 |
- |
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